1. Field of the Invention
The present invention relates generally to the field of electronics and more particularly to the field of multiple die interconnection and data transfer between multiple dies.
2. Description of Related Art
There are situations in which a system, device, node, access point, base station, mobile station and the like will be implemented with multiple dies in a package such as, for example, an application specific integrated circuit (ASIC), field programmable gate array (FPGA) or some other suitable package system. Such multiple die implementations are, for example, common in system development as well as for products without sufficiently high volumes. In contrast to multiple die implementations for low volume products, monolithic die integration is usually preferred for very high volume products. In multiple die implementations, there must be a way to provide communication and interconnection between the dies in the multiple die system design.
One known multiple die data communication link design uses the same data path for data that is transmitted and received between the dies. In non-posted writes and reads [a first command is initiated (a transmit signal) and then a response (a receive signal) is received back], the other potential link users i.e. other circuits for example on the dies, are not able to utilize the link when an access is pending, which leads to a less than optimal or desired throughput. In other words, during the time the link is waiting for response, it is not transmitting any real data and cannot transmit any data until such time as the destination gives the response.
The die's internal signal connection count between functional entities is almost free i.e. there can be literally thousands of signals without any problem. The signal connections between dies are quite expensive, thus the link count is limited and the pin count is heavily optimized. When the functionality is split into two dies, the data communication link between the two dies is often one of the bottlenecks of the design. Some drawbacks presented by the data communication link design include for example, additional latency, limited data throughput and the additional power that is consumed by the receiver and transmitter and the input/output (I/O) design configuration of the link.
An example of an on-chip-interconnect implementation in an application specific integrated circuit is shown in FIG. 1 and generally designated 8. In this example, the functionality is split into two dies. A first die generally designated 10 is connected to a second die generally designated 12 by means of a master-slave link generally designated 14. The first die 10 is configured as the master side and includes an on-chip interconnect design generally designated 10a, a microprocessor 10b, one or more modules 10c, a direct memory access 10d and a master data transfer controller 10e, and an off-die memory 10f, all of which are suitably arranged and interconnected to carry out the intended functionality according to the circuit or system design. The second die 12 is configured as the slave side and includes an on-chip interconnect design 12a, one or more modules 12b and a slave data transfer controller 12c. The same signals are used to transfer data in one direction and the other direction between the two dies 10, 12 over the master-slave link 14. The master-slave link 14 is a half-duplex data communication link and in accordance with half-duplex data communication link operation only one non-burst and one non-posted access can be pending at a time.
In addition, only the master side, which in the example is on die 10 of the master-slave link 14, can initiate a data transfer and this restriction further complicates the system design. The slave side, which in the example is on die 12 needs to raise attention with signals other than the signal provided by the master-slave data link 14. A suitable protocol for the master-slave link implementation must be used for example, for processor accesses through a die boundary further adding to the complexity of the system design. In the solutions such as shown in the example illustrated in FIG. 1, a processing occurring on die 10 may require information from die 12 to carry out an action or operation. In this example, a request is sent from die 10 to die 12 via the half-duplex master-slave link 14. The processing on die 10 must now wait until it receives the requested information from die 12 before proceeding. Because the master-slave half-duplex link 14 can only move information in one direction at a time, die 12 cannot receive additional information requests from die 10 until it responds to the “open” request. Once the die 10 receives the requested information, processing of that particular action or operation can continue to complete the access. In other words, the accesses and responses must complete in the order in which they occur.
Although “off-chip” interconnect solutions such as master-slave half-duplex link connections have been used for example, for connecting code division multiple access (CDMA) or wideband code division multiple access (WCDMA) accelerators to a suitable cooperating application specific integrated circuit (ASIC), these solutions are not satisfactory for data communication between multiple dies, and particularly for systems that are tightly coupled and divided into multiple dies and even more particularly for modern communication systems such as for example, the 3rd Generation Partnership Project (3GPP) Evolved Universal Terrestrial Radio Access Network (EUTRAN).
What is needed therefore is a way to provide data communication between multiple dies that overcomes the design drawbacks of known solutions.